Wireless communication devices, such as mobile phone handsets, require a very high level of integration of hardware and firmware/software in order to achieve the necessary density of functionality, i.e. to realise the necessary functionality in a minimum device volume and at a minimum cost. An optimal wireless communication device design must also minimise power consumption in order to increase the battery call time and/or stand-by time.
Wireless communication devices also incorporate a number of distinct and operably coupled sub-systems, in order to provide the wide variety of functions and operations that a complex wireless communication device needs to perform. Such sub-systems comprise radio frequency power amplification functions, radio frequency integrated circuits (RFIC) comprising radio frequency generation, amplification, filtering, etc. baseband integrated circuits (BBIC) comprising audio circuits, encoding/decoding, (de)modulation logic, processing functions, etc. and memory units.
Interfaces, which are often standardised to allow commonality and increased functionality between different chip-set manufacturers and different handset manufacturers, are defined for communicating between the respective sub-systems.
In the field of mobile phones, a consortium of mobile phone manufacturers has been formed to define various sub-system interfaces, particularly interfaces between variants of second generation of cellular phones (2.xG) when migrating to cover additional, future wireless communication technologies, such as multimode transceivers additionally employing third generation (3G) wideband code division multiple access (WCDMA) technology. This consortium is known as ‘DigRF’, and details of the defined interfaces and functionality thereof, particularly in a multimode mobile phone scenario, can be found on their web-site at www.digrf.com.
In a 3G wireless communication system, a link is established between a mobile terminal, known as the mobile (MS), and a fixed terminal, known as the base station (BS). In order for the MS and the BS to communicate it is necessary that they have (or acquire) a common time reference. Without this common time reference, either the MS or BS will not be able to correctly receive, demodulate and decode the data being transmitted.
In 3G wireless communications, the reference clock of the MS is synchronised to that of the BS through observation of a pilot signal transmitted by the BS that contains clock frequency information. In practice, the synchronisation will not be exact and there will be some residual error between the reference clocks on the MS and the BS. Both the MS and the BS contain local reference clocks, which will typically be accurate to an absolute timing reference within some specified level of tolerance. However, there will still be a small timing error between the MS and BS internal clocks, for example due to propagation delays within timing generation logic, accuracy of a timing reference in both the MS and BS, drift over time of the local timing reference, etc. Thus, as time elapses, the accumulated error from these factors can become significant enough to degrade the performance of the communication link.
One common scheme to sporadically resynchronise the MS and BS time references is to advance or retard the local clock by one complete clock cycle. Typically the baseband controlling element of the MS will analyse the signal received from the BS and will determine whether the local MS clock is fast or slow relative to the BS clock. Upon this determination the baseband in the MS decides whether to advance or retard the time base of the Tx signal or, as is more often the case, just to do nothing. Typically, the MS timing control algorithm will estimate the accumulated timing error between the MS and BS clocks. When the accumulated timing error has reached a preset threshold, a command is sent by the baseband to advance or retard the MS time base.
A known problem is how to best determine whether a timing advance/retard operation is required and thereafter how best to advance or retard the Tx signal.
A number of approaches are known to signal such an advance/retard operation in the DigRF context. One approach is for the BBIC to generate an advance/retard command, which is used by digital baseband circuitry to delay or advance the actual Tx signal sent from the digital baseband (DBB) circuitry to the RF IC. This operation is performed at baseband if the RF transceiver does not implement a variable delay. Typically, in this case, the BBIC will contain some signal processing circuitry that is used to generate the command to be transmitted to the digital baseband circuitry. The advance/retard command can be effected by either deleting an existing sample or inserting an extra sample into the data stream.
Notably, the known prior art is focused on a baseband implementation that determines whether timing advance/retard operation is required, and thereafter a command is sent to either digital baseband circuit or RFIC logic to implement the timing advance/retard operation.
This is complex in that all control is performed by the BBIC and somewhat inflexible by being limited to a command driven implementation, which requires accommodating dedicated communication paths and signals for processor circuits to receive instructions from the BBIC and interpret these instructions to advance/retard logic.
A need therefore exists for an improved wireless communication device, an integrated circuit and a method of synchronisation therefor that may alleviate the aforementioned problems, without increasing complexity.